The present invention relates to a technology of correctly defining a specification of an interface of a circuit module and facilitating connection between circuit modules with the defined specification in an integrated circuit system or a digital system having plural circuit modules connected therewith.
Improvement of integration level of an LSI results in implementing a system LSI in which almost of the system is mounted on a chip. In designing such a large-scale system LSI, by combining ready-made circuit modules with one another, it is possible to reduce the designing cost and the man-month for design work. One of the most significant subjects in this type of designing method is how to reuse those ready-made circuit modules. Many proposals have been made to this subject and some of them have been already realized. For example, by describing the read-made logic circuit in a hardware description language to be logically synthesized, the resulting circuit module does not depend on an LSI manufacturing process. Further, the trial for making the interface standards for connection circuit modules is made by the standardizing association called VSIA (Virtual Socket Interface Alliance).
In the meantime, a trial for facilitating connection of read-made logical circuits, that is, automatically synthesizing a connection circuit between the logical circuits has been described in Roberto Passerone et al. xe2x80x9cAutomatic Synthesis of Interfaces between Incompatible Protocolsxe2x80x9d, pages 8 to 13, at the 35th Design Automation Conference or Andrew Seawright et al. xe2x80x9cSynthesis from Production-Based Specificationsxe2x80x9d, pages 194 to 199, at the 29th Design Automation Conference.
These proposals have described the method of describing an interface operation of a logical circuit in a special language and automatically synthesizing a connection circuit from the description. The trial for describing the interface itself has been proposed in J. A. Nestor et al. xe2x80x9cBehavioral Synthesis with Interfacesxe2x80x9d, pages 112 to 115, at the International Conference on Computer Aided Design in 1986 or Gaetano Borriello et al. xe2x80x9cSynthesis and Optimization of Interface Transducer Logicxe2x80x9d, pages 274 to 277, at the International Conference on Computer Aided Design in 1987.
In order to reuse ready-made circuit modules, the documents to which the designer has traditionally referred are only the manual about one circuit module and the hardware description of the circuit module. The manual has described the specification of the circuit module, that is, the function and the operation of the circuit module explained with reference to the timing charts or the like. The manual, however, merely illustrates the operations described on the charts and one example of behavior of an interface appearing in using a certain function. It does not exhaustively describe all the operations of the circuit module. Further, since the operation is represented only on the chart, in order to verify the feasibility to connect the circuit with the circuit module to be reused, the designer is required to verify if the waveform described on the chart is regenerated.
This verification has been done by the manual work, so that it needs lots of designing steps. Hence, if the designer misunderstand the timing chart, the proper circuit cannot be designed. To avoid this disadvantage, the designer has to correctly understand the manual and in some cases analyze the hardware description for grasping the operation.
According to an aspect of the invention, a computer readable medium is arranged to store a structure and an operation description of a conventional circuit module, distinguish a set of signal values to be taken on a specific time at each I/O terminal relevant to each function of the circuit module by means of identifiers for signals, and at a time store a description about an interface of each function of the hardware description with the combination of the identifiers on a temporal order.
According to another aspect of the invention, a verifying method is executed to verify if two circuit modules are to be connected by doing comparison of a slip of each time point on which a given event takes place between the two circuit modules by using the information stored in the computer readable medium.
According to another aspect of the invention, a method is executed to synthesize a signal pattern by following change of a signal appearing at the I/O terminal of the circuit module on the temporal order by using the information stored in the computer readable medium.